1. Field of the Invention
The invention relates to a multi-part upper electrode for a semiconductor processing plasma reactor and a method of replacing an eroded portion of the multi-part upper electrode.
2. Description of the Related Art
Electrodes used in plasma processing reactors for processing semiconductor substrates such as silicon wafers are disclosed in U.S. Pat. Nos. 5,074,456 and 5,569,356, the disclosures of which are hereby incorporated by reference.
Dry plasma etching, reactive ion etching, and ion milling techniques were developed in order to overcome numerous limitations associated with chemical etching of semiconductor wafers. Plasma etching, in particular, allows the vertical etch rate to be made much greater than the horizontal etch rate so that the resulting aspect ratio (i.e., the height to width ratio of the resulting notch) of the etched features can be adequately controlled. In fact, plasma etching enables very fine features with high aspect ratios to be formed in films over 1 micrometer in thickness.
During the plasma etching process, a plasma is formed above the masked surface of the wafer by adding large amounts of energy to a gas at relatively low pressure, resulting in ionizing the gas. By adjusting the electrical potential of the substrate to be etched, charged species in the plasma can be directed to impinge substantially normally upon the wafer, wherein materials in the unmasked regions of the wafer are removed.
The etching process can often be made more effective by using gases that are chemically reactive with the material being etched. So called “reactive ion etching” combines the energetic etching effects of the plasma with the chemical etching effect of the gas. However, many chemically active agents have been found to cause excessive electrode wear.
It is desirable to evenly distribute the plasma over the surface of the wafer in order to obtain uniform etching rates over the entire surface of the wafer. For example, U.S. Pat. Nos. 4,595,484, 4,792,378, 4,820,371, 4,960,468 disclose showerhead electrodes for distributing gas through a number of holes in the electrodes. These patents generally describe gas distribution plates having an arrangement of apertures tailored to provide a uniform flow of gas vapors to a semiconductor wafer.
A reactive ion etching system typically consists of an etching chamber with an upper electrode or grounded electrode and a lower electrode or RF electrode positioned therein. The wafer to be etched is covered by a suitable mask and placed directly on the RF electrode. The wafer is negatively biased as a result of its interaction with the plasma. A chemically reactive gas such as CF4, CHF3, CClF3, and SF6 or mixtures thereof with O, N2, He, or Ar is introduced into the etching chamber and maintained at a pressure which is typically in the millitorr range. The grounded electrode is provided with gas holes which permit the gas to be uniformly dispersed through the electrode into the chamber. The electric field established between the grounded electrode and the RF electrode will dissociate the reactive gas forming a plasma. The surface of the wafer is etched by chemical interaction with the active ions and by momentum transfer of the ions striking the surface of the wafer. The electric field created by the electrodes will attract the ions to the wafer, causing the ions to strike the surface in a predominantly vertical direction so that the process produces well-defined vertically etched side walls.
The exposed surfaces of the upper electrode are also etched during wafer processing. Electrode loss or etching results in a need to periodically replace the upper electrode. Thus, it would be desirable to make electrode replacement simple and economical.
As substrate size increases it is important to ensure uniform etching and deposition with increasingly large wafer sizes and correspondingly large electrode sizes. The industry move from 200 mm to 300 mm wafers allows manufacturers to double their wafer area and chip output. The increase in wafer size results in certain difficulties in scaling up of the wafer processing tools. For example, single crystal silicon boules used to make some upper electrodes are manufactured in sizes up to 15 inches in diameter. The larger diameter single crystal silicon electrodes are difficult to manufacture with the desired low impurity levels. Thus, the large diameter single crystal silicon electrodes are costly.
An upper showerhead electrode 10 and a smaller lower electrode 12 for a single wafer etch chamber are shown in FIG. 1. The configuration of FIG. 1 shows an electrode configuration for a capacitively coupled, confined plasma etch chamber with one electrode powered by two RF sources at different frequencies and the other electrode grounded. The lower electrode 12 is a flat electrode on which a wafer W is supported. The lower electrode 12 is spaced 1 to 2 cm below the upper electrode 10. In this configuration, the upper electrode 10 has a step 14 ground into the electrode providing an electrode with a thinner inner portion, an angled step portion, and a thicker outer perimeter. The step 14 has been designed to provide etch rate uniformity at the edge of the chip.
The electrode 10 has a diameter of 15″ to accommodate 300 mm wafers. An extension 16 of the electrode 10 is provided which extends the electrode from 15″ to 17″ and is constructed of a plurality of silicon segments. This configuration requires a single crystal silicon electrode 10 having a diameter of 15″ which is then ground to form the step 14. This large diameter electrode 10 is quite costly and requires periodic replacement due to wear.